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| author | Craig Topper <craig.topper@intel.com> | 2017-12-04 05:38:44 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-04 05:38:44 +0000 |
| commit | 1151facf76bd3b10353075e7a28f491a21b8d3cc (patch) | |
| tree | 70057531a1187fb69de0e252fecc48471f134afa /llvm/lib | |
| parent | 67217d7eb474982c34d807acae60708466b9f519 (diff) | |
| download | bcm5719-llvm-1151facf76bd3b10353075e7a28f491a21b8d3cc.tar.gz bcm5719-llvm-1151facf76bd3b10353075e7a28f491a21b8d3cc.zip | |
[X86] Don't turn UINT_TO_FP into SINT_TO_FP during lowering.
We already do this as a DAG combine. The version during lowering can only trigger if known bits changes something that improves known bits analysis. But this means we should be improving known bits analysis to work on the unlowered form instead.
llvm-svn: 319640
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 503e8467085..48e6c31be6b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15820,12 +15820,6 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SDLoc dl(Op); auto PtrVT = getPointerTy(DAG.getDataLayout()); - // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't - // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform - // the optimization here. - if (DAG.SignBitIsZero(N0)) - return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); - if (Op.getSimpleValueType().isVector()) return lowerUINT_TO_FP_vec(Op, DAG); |
