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author | Amara Emerson <aemerson@apple.com> | 2019-01-29 21:19:33 +0000 |
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committer | Amara Emerson <aemerson@apple.com> | 2019-01-29 21:19:33 +0000 |
commit | 102c9ed768d534189bb51b53212dbba7eee9e412 (patch) | |
tree | 805e54caaa3524ce8d346b04eccdaaa951c684d2 /llvm/lib | |
parent | a4c33ecd78b3b8e3ceca3e6c96626218304110f5 (diff) | |
download | bcm5719-llvm-102c9ed768d534189bb51b53212dbba7eee9e412.tar.gz bcm5719-llvm-102c9ed768d534189bb51b53212dbba7eee9e412.zip |
[AArch64][GlobalISel] Unmerge into scalars from a vector should use FPR bank.
This currently shows up as a selection fallback since the dest regs were given
GPR banks but the source was a vector FPR reg.
Differential Revision: https://reviews.llvm.org/D57408
llvm-svn: 352545
Diffstat (limited to 'llvm/lib')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index bbf4e4e0571..23d7e18436d 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -669,7 +669,11 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { &AArch64::FPRRegBank; }; - if (any_of(MRI.use_instructions(MI.getOperand(0).getReg()), + LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg()); + // UNMERGE into scalars from a vector should always use FPR. + // Likewise if any of the uses are FP instructions. + if (SrcTy.isVector() || + any_of(MRI.use_instructions(MI.getOperand(0).getReg()), [&](MachineInstr &MI) { return HasFPConstraints(MI); })) { // Set the register bank of every operand to FPR. for (unsigned Idx = 0, NumOperands = MI.getNumOperands(); |