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authorDaniel Sanders <daniel.sanders@imgtec.com>2016-03-22 14:29:53 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2016-03-22 14:29:53 +0000
commit0f17d0da4a9c3da0e2488eab1aee63adfaf8504f (patch)
tree43a3f53e1a2b1bbb4902a20c2c03be5c163a8827 /llvm/lib
parent946dee3b5b5469ed4161efd63a0c44968b07fcf1 (diff)
downloadbcm5719-llvm-0f17d0da4a9c3da0e2488eab1aee63adfaf8504f.tar.gz
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[mips] Range check simm5.
Summary: We can't check the error message for this one because there's another lw/sw available that covers a larger range. We therefore check the transition between the two sizes. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D18144 llvm-svn: 264054
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp3
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td6
-rw-r--r--llvm/lib/Target/Mips/MipsMSAInstrInfo.td1
3 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 32c6ffd3440..41d8d2484b8 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -3729,6 +3729,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_UImm5_0:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected 5-bit unsigned immediate");
+ case Match_SImm5_0:
+ return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+ "expected 5-bit signed immediate");
case Match_UImm5_1:
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
"expected immediate in range 1 .. 32");
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 8fa1c83b26b..3de29995869 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -507,8 +507,10 @@ def ConstantUImm5Plus1AsmOperandClass
5, [ConstantUImm5Plus32NormalizeAsmOperandClass], 1>;
def ConstantUImm5AsmOperandClass
: ConstantUImmAsmOperandClass<5, [ConstantUImm5Plus1AsmOperandClass]>;
+def ConstantSImm5AsmOperandClass
+ : ConstantSImmAsmOperandClass<5, [ConstantUImm5AsmOperandClass]>;
def ConstantUImm4AsmOperandClass
- : ConstantUImmAsmOperandClass<4, [ConstantUImm5AsmOperandClass]>;
+ : ConstantUImmAsmOperandClass<4, [ConstantSImm5AsmOperandClass]>;
def ConstantSImm4AsmOperandClass
: ConstantSImmAsmOperandClass<4, [ConstantUImm4AsmOperandClass]>;
def ConstantUImm3AsmOperandClass
@@ -724,7 +726,7 @@ foreach I = {1, 2, 3, 4, 5, 6, 8} in
}
// Signed operands
-foreach I = {4} in
+foreach I = {4, 5} in
def simm # I : Operand<i32> {
let DecoderMethod = "DecodeSImmWithOffset<" # I # ">";
let ParserMatchClass =
diff --git a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
index 5ecc3b3fb66..89e530b8e10 100644
--- a/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -70,7 +70,6 @@ def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
// Operands
-def simm5 : Operand<i32>;
def vsplat_simm5 : Operand<vAny>;
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