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| author | Evan Cheng <evan.cheng@apple.com> | 2006-10-30 08:02:39 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-10-30 08:02:39 +0000 |
| commit | 0d41d19427695d248de76076bf522125f3d8b84d (patch) | |
| tree | f00a96479d69ffc75a6175dfc14b8a71537f0fff /llvm/lib | |
| parent | 84a28d4e76553e124af965888b01d4874e8d821e (diff) | |
| download | bcm5719-llvm-0d41d19427695d248de76076bf522125f3d8b84d.tar.gz bcm5719-llvm-0d41d19427695d248de76076bf522125f3d8b84d.zip | |
All targets expand BR_JT for now.
llvm-svn: 31294
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/IA64/IA64ISelLowering.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/X86/X86ISelLowering.cpp | 1 |
6 files changed, 11 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp index 7221818d175..3674bf1f693 100644 --- a/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -73,7 +73,8 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setOperationAction(ISD::MEMSET, MVT::Other, Expand); - setOperationAction(ISD::BRIND, MVT::i32, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BRIND, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_CC, MVT::f64, Custom); diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index f5372e126c3..cfc99957c72 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -62,7 +62,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) setStoreXAction(MVT::i1, Promote); - // setOperationAction(ISD::BRIND, MVT::i64, Expand); + // setOperationAction(ISD::BRIND, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::Other, Expand); setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); diff --git a/llvm/lib/Target/IA64/IA64ISelLowering.cpp b/llvm/lib/Target/IA64/IA64ISelLowering.cpp index 83894eebdbf..e9176e1bf28 100644 --- a/llvm/lib/Target/IA64/IA64ISelLowering.cpp +++ b/llvm/lib/Target/IA64/IA64ISelLowering.cpp @@ -44,7 +44,8 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand); setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand); - setOperationAction(ISD::BRIND , MVT::i64, Expand); + setOperationAction(ISD::BRIND , MVT::Other, Expand); + setOperationAction(ISD::BR_JT , MVT::Other, Expand); setOperationAction(ISD::BR_CC , MVT::Other, Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4285b682b6b..df4e9acfa74 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -107,6 +107,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) // PowerPC does not have BRCOND which requires SetCC setOperationAction(ISD::BRCOND, MVT::Other, Expand); + + setOperationAction(ISD::BR_JT, MVT::Other, Expand); // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 299cf06c438..e6e036943bd 100644 --- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -174,7 +174,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) // Sparc doesn't have BRCOND either, it has BR_CC. setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRIND, MVT::i32, Expand); + setOperationAction(ISD::BRIND, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::BR_CC, MVT::i32, Custom); setOperationAction(ISD::BR_CC, MVT::f32, Custom); setOperationAction(ISD::BR_CC, MVT::f64, Custom); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d442a18850b..0b8550686c3 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -146,6 +146,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); + setOperationAction(ISD::BR_JT , MVT::Other, Expand); setOperationAction(ISD::BRCOND , MVT::Other, Custom); setOperationAction(ISD::BR_CC , MVT::Other, Expand); setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); |
