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| author | Hal Finkel <hfinkel@anl.gov> | 2015-01-09 01:29:29 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2015-01-09 01:29:29 +0000 |
| commit | 0ce7f372e5016999b3a56cb2a0eb8784cd4179af (patch) | |
| tree | 1cd6ea4329deb6054eddde1acd2f21ebd5c565b6 /llvm/lib | |
| parent | 685b1803abc396f2d05238005812f80ea4903adf (diff) | |
| download | bcm5719-llvm-0ce7f372e5016999b3a56cb2a0eb8784cd4179af.tar.gz bcm5719-llvm-0ce7f372e5016999b3a56cb2a0eb8784cd4179af.zip | |
[DAGCombine] Remainder of fix to r225380 (More FMA folding opportunities)
As pointed out by Aditya (and Owen), when we elide an FP extend to form an FMA,
we need to extend the incoming operands so that the resulting node will really
be legal. This is currently enabled only for PowerPC, and it happens to work
there regardless, but this should fix the functionality for everyone else
should anyone else wish to use it.
llvm-svn: 225492
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 34 |
1 files changed, 24 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 08549d00cf8..4f570329979 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6928,7 +6928,10 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { SDValue N00 = N0.getOperand(0); if (N00.getOpcode() == ISD::FMUL) return DAG.getNode(ISD::FMA, SDLoc(N), VT, - N00.getOperand(0), N00.getOperand(1), N1); + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N00.getOperand(0)), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N00.getOperand(1)), N1); } // fold (fadd x, (fpext (fmul y, z)), z) -> (fma y, z, x) @@ -6937,7 +6940,10 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { SDValue N10 = N1.getOperand(0); if (N10.getOpcode() == ISD::FMUL) return DAG.getNode(ISD::FMA, SDLoc(N), VT, - N10.getOperand(0), N10.getOperand(1), N0); + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N10.getOperand(0)), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N10.getOperand(1)), N0); } } } @@ -7073,8 +7079,10 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { SDValue N00 = N0.getOperand(0); if (N00.getOpcode() == ISD::FMUL) return DAG.getNode(ISD::FMA, SDLoc(N), VT, - N00.getOperand(0), - N00.getOperand(1), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N00.getOperand(0)), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N00.getOperand(1)), DAG.getNode(ISD::FNEG, SDLoc(N), VT, N1)); } @@ -7085,8 +7093,10 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { if (N10.getOpcode() == ISD::FMUL) return DAG.getNode(ISD::FMA, SDLoc(N), VT, DAG.getNode(ISD::FNEG, SDLoc(N), VT, - N10.getOperand(0)), - N10.getOperand(1), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), + VT, N10.getOperand(0))), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N10.getOperand(1)), N0); } @@ -7099,8 +7109,10 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { if (N000.getOpcode() == ISD::FMUL) { return DAG.getNode(ISD::FMA, dl, VT, DAG.getNode(ISD::FNEG, dl, VT, - N000.getOperand(0)), - N000.getOperand(1), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), + VT, N000.getOperand(0))), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N000.getOperand(1)), DAG.getNode(ISD::FNEG, dl, VT, N1)); } } @@ -7115,8 +7127,10 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { if (N000.getOpcode() == ISD::FMUL) { return DAG.getNode(ISD::FMA, dl, VT, DAG.getNode(ISD::FNEG, dl, VT, - N000.getOperand(0)), - N000.getOperand(1), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), + VT, N000.getOperand(0))), + DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, + N000.getOperand(1)), DAG.getNode(ISD::FNEG, dl, VT, N1)); } } |
