Two more test cases: or_ops.ll (arithmetic or operations) and vecinsert.ll

(vector insertions)

llvm-svn: 45216

2 files changed, 5 insertions, 6 deletions

diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
index 253fafb8e95..7d221877512 100644
--- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -880,13 +880,12 @@ LowerConstantFP(SDOperand Op, SelectionDAG &DAG) {
   assert((FP != 0) &&
 	 "LowerConstantFP: Node is not ConstantFPSDNode");
 
-  const APFloat &apf = FP->getValueAPF();
-
   if (VT == MVT::f32) {
+    float targetConst = FP->getValueAPF().convertToFloat();
     return DAG.getNode(SPUISD::SFPConstant, VT,
-		       DAG.getTargetConstantFP(apf.convertToFloat(), VT));
+		       DAG.getTargetConstantFP(targetConst, VT));
   } else if (VT == MVT::f64) {
-    uint64_t dbits = DoubleToBits(apf.convertToDouble());
+    uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble());
     return DAG.getNode(ISD::BIT_CONVERT, VT,
 		       LowerConstant(DAG.getConstant(dbits, MVT::i64), DAG));
   }
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
index efd45f56dcd..5c2bd52d501 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -98,13 +98,13 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
     destReg = MI.getOperand(0).getReg();
     return true;
 #endif
-    // case SPU::ORv16i8_i8:
+  case SPU::ORv16i8_i8:
   case SPU::ORv8i16_i16:
   case SPU::ORv4i32_i32:
   case SPU::ORv2i64_i64:
   case SPU::ORv4f32_f32:
   case SPU::ORv2f64_f64:
-    // case SPU::ORi8_v16i8:
+  case SPU::ORi8_v16i8:
   case SPU::ORi16_v8i16:
   case SPU::ORi32_v4i32:
   case SPU::ORi64_v2i64: