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| author | Misha Brukman <brukman+llvm@gmail.com> | 2003-05-30 20:15:59 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2003-05-30 20:15:59 +0000 |
| commit | 0757de607a7a0ef57ee97ac45e9d80fad5bfb743 (patch) | |
| tree | 894ad1de5dc24bd0f675050d210148c311745da5 /llvm/lib | |
| parent | 87473772928e6d619bb85f1ca8b7382a42da0951 (diff) | |
| download | bcm5719-llvm-0757de607a7a0ef57ee97ac45e9d80fad5bfb743.tar.gz bcm5719-llvm-0757de607a7a0ef57ee97ac45e9d80fad5bfb743.zip | |
Fixed the namespace to match SparcInternals.h; added notes on some missing
sections of instructions.
llvm-svn: 6448
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcV9.td | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/llvm/lib/Target/Sparc/SparcV9.td b/llvm/lib/Target/Sparc/SparcV9.td index fd7a0a995ed..008b0637ee7 100644 --- a/llvm/lib/Target/Sparc/SparcV9.td +++ b/llvm/lib/Target/Sparc/SparcV9.td @@ -13,7 +13,7 @@ class InstV9 : Instruction { // Sparc instruction baseline field bits<32> Inst; - set Namespace = "SparcV9"; + set Namespace = "V9"; bits<2> op; set Inst{31-30} = op; // Top two bits are the 'op' field @@ -202,7 +202,16 @@ def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r -// Section A.24: Jump and Link +// FIXME: A.20: Flush Instruction Memory - p167 +// FIXME: A.21: Flush Register Windows - p169 + +// A.22: Illegal instruction Trap - p170 +// Not used + +// A.23: Implementation-Dependent Instructions - p171 +// Not used + +// Section A.24: Jump and Link - p172 // Mimicking the Sparc's instr def... def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [r+r], r def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [r+i], r @@ -319,11 +328,14 @@ def FMOVFULE : F4_7<2, 0b110101, 0b1110, "fmovfule">; // fmovfule r, r def FMOVFO : F4_7<2, 0b110101, 0b1111, "fmovfo">; // fmovfo r, r #endif -// Section A.34: Move F-P Register on Integer Register (FMOVr) +// FIXME: Section A.34: Move F-P Register on Integer Register (FMOVr) + -// Section A.35: Move Integer Register on Condition (MOVcc) +// FIXME: Section A.35: Move Integer Register on Condition (MOVcc) + + +// FIXME: Section A.36: Move Integer Register on Register Condition (MOVR) -// Section A.36: Move Integer Register on Register Condition (MOVR) // Section A.37: Multiply and Divide (64-bit) - p199 def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r @@ -425,6 +437,7 @@ def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r // Section A.50: FIXME + // Section A.51: FIXME // Section A.52: Store Floating-point -p225 |
