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| author | Diana Picus <diana.picus@linaro.org> | 2017-07-11 11:47:45 +0000 |
|---|---|---|
| committer | Diana Picus <diana.picus@linaro.org> | 2017-07-11 11:47:45 +0000 |
| commit | 069da27f49a1f25ec0d6518cc13732c8d40ae228 (patch) | |
| tree | a8816a34d4457eb9f038f49df93a1ee262ee51f1 /llvm/lib | |
| parent | 4a9cfc82676bed178bf39fd5b12f4f389a0c0782 (diff) | |
| download | bcm5719-llvm-069da27f49a1f25ec0d6518cc13732c8d40ae228.tar.gz bcm5719-llvm-069da27f49a1f25ec0d6518cc13732c8d40ae228.zip | |
[ARM] GlobalISel: Add reg mapping for s64 G_FCMP
Map the result into GPR and the operands into FPR.
llvm-svn: 307653
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp index 8e57c029e76..0f0e0e2df5f 100644 --- a/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -279,16 +279,20 @@ ARMRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const { } case G_FCMP: { LLT Ty1 = MRI.getType(MI.getOperand(2).getReg()); - (void)Ty1; LLT Ty2 = MRI.getType(MI.getOperand(3).getReg()); (void)Ty2; assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP"); - assert(Ty1.getSizeInBits() == 32 && "Unsupported size for G_FCMP"); - assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_FCMP"); + assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() && + "Mismatched operand sizes for G_FCMP"); + + unsigned Size = Ty1.getSizeInBits(); + assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP"); + + auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx] + : &ARM::ValueMappings[ARM::DPR3OpsIdx]; OperandsMapping = getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr, - &ARM::ValueMappings[ARM::SPR3OpsIdx], - &ARM::ValueMappings[ARM::SPR3OpsIdx]}); + FPRValueMapping, FPRValueMapping}); break; } case G_MERGE_VALUES: { |
