[X86] Name the MMX phaddd instruction with 3 Ds instead of just 2. NFC

llvm-svn: 323403

8 files changed, 13 insertions, 13 deletions

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index 5d33800a942..ba5f0f2130f 100644
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -1424,9 +1424,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
+    { X86::MMX_PHADDDrr,      X86::MMX_PHADDDrm,      0 },
     { X86::MMX_PHADDSWrr,     X86::MMX_PHADDSWrm,     0 },
     { X86::MMX_PHADDWrr,      X86::MMX_PHADDWrm,      0 },
-    { X86::MMX_PHADDrr,       X86::MMX_PHADDrm,       0 },
     { X86::MMX_PHSUBDrr,      X86::MMX_PHSUBDrm,      0 },
     { X86::MMX_PHSUBSWrr,     X86::MMX_PHSUBSWrm,     0 },
     { X86::MMX_PHSUBWrr,      X86::MMX_PHSUBWrm,      0 },
diff --git a/llvm/lib/Target/X86/X86InstrMMX.td b/llvm/lib/Target/X86/X86InstrMMX.td
index f70c194bd8d..f6bff658e56 100644
--- a/llvm/lib/Target/X86/X86InstrMMX.td
+++ b/llvm/lib/Target/X86/X86InstrMMX.td
@@ -388,7 +388,7 @@ defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w,
 
 defm MMX_PHADDW  : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w,
                                    MMX_PHADDSUBW>;
-defm MMX_PHADD   : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
+defm MMX_PHADDD  : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d,
                                    MMX_PHADDSUBD>;
 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw,
                                    MMX_PHADDSUBW>;
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index b61c389b667..e60471409ff 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -1378,9 +1378,9 @@ def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
   let NumMicroOps = 3;
   let ResourceCycles = [2,1];
 }
+def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr")>;
 def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDSWrr")>;
 def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDrr")>;
 def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBDrr")>;
 def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBSWrr")>;
 def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHSUBWrr")>;
@@ -2709,9 +2709,9 @@ def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
   let NumMicroOps = 4;
   let ResourceCycles = [2,1,1];
 }
+def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm")>;
 def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDSWrm")>;
 def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDrm")>;
 def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBDrm")>;
 def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBSWrm")>;
 def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHSUBWrm")>;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index 7d45de5b95d..4e2b078f23f 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -2741,9 +2741,9 @@ def HWWriteResGroup56 : SchedWriteRes<[HWPort5,HWPort15]> {
   let NumMicroOps = 3;
   let ResourceCycles = [2,1];
 }
+def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDDrr")>;
 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDSWrr")>;
 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHADDrr")>;
 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBDrr")>;
 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBSWrr")>;
 def: InstRW<[HWWriteResGroup56], (instregex "MMX_PHSUBWrr")>;
@@ -2857,9 +2857,9 @@ def HWWriteResGroup64 : SchedWriteRes<[HWPort5,HWPort23,HWPort15]> {
   let NumMicroOps = 4;
   let ResourceCycles = [2,1,1];
 }
+def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDDrm")>;
 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDSWrm")>;
 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHADDrm")>;
 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBDrm")>;
 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBSWrm")>;
 def: InstRW<[HWWriteResGroup64], (instregex "MMX_PHSUBWrm")>;
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td
index 28a787a6db8..025240e48ed 100644
--- a/llvm/lib/Target/X86/X86SchedSandyBridge.td
+++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td
@@ -1043,9 +1043,9 @@ def SBWriteResGroup24 : SchedWriteRes<[SBPort15]> {
   let NumMicroOps = 3;
   let ResourceCycles = [3];
 }
+def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDDrr")>;
 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDSWrr")>;
 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHADDrr")>;
 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBDrr")>;
 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBSWrr")>;
 def: InstRW<[SBWriteResGroup24], (instregex "MMX_PHSUBWrr")>;
@@ -2066,9 +2066,9 @@ def SBWriteResGroup80 : SchedWriteRes<[SBPort23,SBPort15]> {
   let NumMicroOps = 4;
   let ResourceCycles = [1,3];
 }
+def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDDrm")>;
 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDSWrm")>;
 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHADDrm")>;
 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBDrm")>;
 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBSWrm")>;
 def: InstRW<[SBWriteResGroup80], (instregex "MMX_PHSUBWrm")>;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index 895f19b61b0..7135f8b2a7d 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1367,8 +1367,8 @@ def SKLWriteResGroup37 : SchedWriteRes<[SKLPort5,SKLPort05]> {
   let NumMicroOps = 3;
   let ResourceCycles = [2,1];
 }
+def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDDrr")>;
 def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHADDrr")>;
 def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBDrr")>;
 def: InstRW<[SKLWriteResGroup37], (instregex "MMX_PHSUBWrr")>;
 
@@ -2765,8 +2765,8 @@ def SKLWriteResGroup113 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort05]> {
   let NumMicroOps = 4;
   let ResourceCycles = [2,1,1];
 }
+def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDDrm")>;
 def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHADDrm")>;
 def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBDrm")>;
 def: InstRW<[SKLWriteResGroup113], (instregex "MMX_PHSUBWrm")>;
 
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
index 6edd7bf4f0f..b934022bf8c 100755
--- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td
@@ -2173,8 +2173,8 @@ def SKXWriteResGroup39 : SchedWriteRes<[SKXPort5,SKXPort05]> {
   let NumMicroOps = 3;
   let ResourceCycles = [2,1];
 }
+def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDDrr")>;
 def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDWrr")>;
-def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHADDrr")>;
 def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBDrr")>;
 def: InstRW<[SKXWriteResGroup39], (instregex "MMX_PHSUBWrr")>;
 
@@ -4534,8 +4534,8 @@ def SKXWriteResGroup124 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort05]> {
   let NumMicroOps = 4;
   let ResourceCycles = [2,1,1];
 }
+def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDDrm")>;
 def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDWrm")>;
-def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHADDrm")>;
 def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBDrm")>;
 def: InstRW<[SKXWriteResGroup124], (instregex "MMX_PHSUBWrm")>;
 
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td
index aa79dacf3dc..2aea14d5de9 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver1.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td
@@ -1067,7 +1067,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>;
 
 // HADD, HSUB PS/PD
 // PHADD|PHSUB (S) W/D.
-def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W?)r(r|m)",
+def : InstRW<[WriteMicrocoded], (instregex "MMX_PHADD(W|D)r(r|m)",
                                "MMX_PHADDSWr(r|m)",
                                "MMX_PHSUB(W|D)r(r|m)",
                                "MMX_PHSUBSWrr",