diff options
| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-03-02 18:10:59 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2017-03-02 18:10:59 +0000 |
| commit | 056c945a5df7c28ecc1963813a2373b343dd2258 (patch) | |
| tree | 58c606cfbd725d532f7fb7b3b7233a7c83ac37c5 /llvm/lib | |
| parent | 5db6a947a2b00dce702543d066cfde2c5b823cfa (diff) | |
| download | bcm5719-llvm-056c945a5df7c28ecc1963813a2373b343dd2258.tar.gz bcm5719-llvm-056c945a5df7c28ecc1963813a2373b343dd2258.zip | |
[Hexagon] Skip blocks that define vector predicate registers in early-if
llvm-svn: 296777
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index d7c726bb36c..c1891674721 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -383,8 +383,14 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) unsigned R = MO.getReg(); if (!TargetRegisterInfo::isVirtualRegister(R)) continue; - if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass) - continue; + switch (MRI->getRegClass(R)->getID()) { + case Hexagon::PredRegsRegClassID: + case Hexagon::VecPredRegsRegClassID: + case Hexagon::VecPredRegs128BRegClassID: + break; + default: + continue; + } for (auto U = MRI->use_begin(R); U != MRI->use_end(); ++U) if (U->getParent()->isPHI()) return false; |
