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authorMatt Arsenault <Matthew.Arsenault@amd.com>2016-03-01 18:01:37 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2016-03-01 18:01:37 +0000
commit03dac8d8e48c2acd3517c028ebbbdeea0628a706 (patch)
treeae32e6ef19d67b295465178f615f02ffe67bae73 /llvm/lib
parente55c1658ea4b2945942ab3d3646258101c75e2e2 (diff)
downloadbcm5719-llvm-03dac8d8e48c2acd3517c028ebbbdeea0628a706.tar.gz
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DAGCombiner: Turn extract of bitcasted integer into truncate
This reduces the number of bitcast nodes and generally cleans up the DAG when bitcasting between integers and vectors everywhere. llvm-svn: 262358
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp8
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp19
2 files changed, 20 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 3346ea7fb54..d2d48ea936b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12180,6 +12180,14 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// converts.
}
+ // extract_vector_elt (v2i32 (bitcast i64:x)), 0 -> i32 (trunc i64:x)
+ if (ConstEltNo && InVec.getOpcode() == ISD::BITCAST && InVec.hasOneUse() &&
+ ConstEltNo->isNullValue()) {
+ SDValue BCSrc = InVec.getOperand(0);
+ if (BCSrc.getValueType().isScalarInteger())
+ return DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, BCSrc);
+ }
+
// Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
// We only perform this optimization before the op legalization phase because
// we may introduce new vector instructions which are not backed by TD
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 58de94c9ef7..5fa7f73f57c 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24850,13 +24850,7 @@ static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
N->getValueType(0) == MVT::i32 &&
InputVector.getValueType() == MVT::v2i32) {
-
- // The bitcast source is a direct mmx result.
SDValue MMXSrc = InputVector.getNode()->getOperand(0);
- if (MMXSrc.getValueType() == MVT::x86mmx)
- return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
- N->getValueType(0),
- InputVector.getNode()->getOperand(0));
// The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
@@ -27940,11 +27934,22 @@ static SDValue combineVectorTruncation(SDNode *N, SelectionDAG &DAG,
static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
+
+ SDValue Src = N->getOperand(0);
+
// Try to detect AVG pattern first.
- if (SDValue Avg = detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG,
+ if (SDValue Avg = detectAVGPattern(Src, N->getValueType(0), DAG,
Subtarget, SDLoc(N)))
return Avg;
+ // The bitcast source is a direct mmx result.
+ // Detect bitcasts between i32 to x86mmx
+ if (Src.getOpcode() == ISD::BITCAST && N->getValueType(0) == MVT::i32) {
+ SDValue BCSrc = Src.getOperand(0);
+ if (BCSrc.getValueType() == MVT::x86mmx)
+ return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(N), MVT::i32, BCSrc);
+ }
+
return combineVectorTruncation(N, DAG, Subtarget);
}
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