[MIPS GlobalISel] Select instructions to load and store i32 on stack

Add code for selection of G_LOAD, G_STORE, G_GEP, G_FRAMEINDEX and
G_CONSTANT. Support loads and stores of i32 values.

Patch by Petar Avramovic.

Differential Revision: https://reviews.llvm.org/D48957

llvm-svn: 337168

3 files changed, 88 insertions, 2 deletions

diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index a07940b5538..af0ac006bc9 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -107,8 +107,72 @@ bool MipsInstructionSelector::select(MachineInstr &I,
   if (selectImpl(I, CoverageInfo)) {
     return true;
   }
-  // We didn't select anything.
-  return false;
+
+  MachineInstr *MI = nullptr;
+  using namespace TargetOpcode;
+
+  switch (I.getOpcode()) {
+  case G_GEP: {
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
+             .add(I.getOperand(0))
+             .add(I.getOperand(1))
+             .add(I.getOperand(2));
+    break;
+  }
+  case G_FRAME_INDEX: {
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
+             .add(I.getOperand(0))
+             .add(I.getOperand(1))
+             .addImm(0);
+    break;
+  }
+  case G_STORE:
+  case G_LOAD: {
+    const unsigned DestReg = I.getOperand(0).getReg();
+    const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID();
+    const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
+
+    if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32)
+      return false;
+
+    const unsigned NewOpc = I.getOpcode() == G_STORE ? Mips::SW : Mips::LW;
+
+    MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(NewOpc))
+             .add(I.getOperand(0))
+             .add(I.getOperand(1))
+             .addImm(0)
+             .addMemOperand(*I.memoperands_begin());
+    break;
+  }
+  case G_CONSTANT: {
+    int Imm = I.getOperand(1).getCImm()->getValue().getLimitedValue();
+    unsigned LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+    MachineInstr *LUi, *ORi;
+
+    LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
+              .addDef(LUiReg)
+              .addImm(Imm >> 16);
+
+    ORi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ORi))
+              .addDef(I.getOperand(0).getReg())
+              .addUse(LUiReg)
+              .addImm(Imm & 0xFFFF);
+
+    if (!constrainSelectedInstRegOperands(*LUi, TII, TRI, RBI))
+      return false;
+    if (!constrainSelectedInstRegOperands(*ORi, TII, TRI, RBI))
+      return false;
+
+    I.eraseFromParent();
+    return true;
+  }
+
+  default:
+    return false;
+  }
+
+  I.eraseFromParent();
+  return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
 }
 
 namespace llvm {
diff --git a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
index e85cccbdba9..3e2fcd6122a 100644
--- a/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsLegalizerInfo.cpp
@@ -20,9 +20,22 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   using namespace TargetOpcode;
 
   const LLT s32 = LLT::scalar(32);
+  const LLT p0 = LLT::pointer(0, 32);
 
   getActionDefinitionsBuilder(G_ADD).legalFor({s32});
 
+  getActionDefinitionsBuilder({G_LOAD, G_STORE})
+      .legalFor({{s32, p0}});
+
+  getActionDefinitionsBuilder(G_CONSTANT)
+      .legalFor({s32});
+
+  getActionDefinitionsBuilder(G_GEP)
+      .legalFor({{p0, s32}});
+
+  getActionDefinitionsBuilder(G_FRAME_INDEX)
+      .legalFor({p0});
+
   computeTables();
   verify(*ST.getInstrInfo());
 }
diff --git a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
index 90ae7a8a87f..cef21f44720 100644
--- a/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
@@ -58,6 +58,7 @@ const RegisterBank &MipsRegisterBankInfo::getRegBankFromRegClass(
   case Mips::GPR32RegClassID:
   case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID:
   case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID:
+  case Mips::SP32RegClassID:
     return getRegBank(Mips::GPRBRegBankID);
   default:
     llvm_unreachable("Register class not supported");
@@ -80,8 +81,16 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 
   switch (Opc) {
   case G_ADD:
+  case G_LOAD:
+  case G_STORE:
+  case G_GEP:
     OperandsMapping = &Mips::ValueMappings[Mips::GPRIdx];
     break;
+  case G_CONSTANT:
+  case G_FRAME_INDEX:
+    OperandsMapping =
+        getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
+    break;
   default:
     return getInvalidInstructionMapping();
   }