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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-05 17:27:39 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-12-05 17:27:39 +0000 |
| commit | 01785bb063f245cc43e1c537301a8b4a6b7bf19d (patch) | |
| tree | d3053a88be0c726f93491811d8ee833352fb318c /llvm/lib | |
| parent | 9c8ebeb03d53ecc77281786d14cacd552dee1d6d (diff) | |
| download | bcm5719-llvm-01785bb063f245cc43e1c537301a8b4a6b7bf19d.tar.gz bcm5719-llvm-01785bb063f245cc43e1c537301a8b4a6b7bf19d.zip | |
[Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions.
llvm-svn: 223482
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 94448f74a08..53124e80ea9 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -319,6 +319,7 @@ multiclass ZXTB_base <string mnemonic, bits<3> minOp> { } } +let isCodeGenOnly=0 in defm zxtb : ZXTB_base<"zxtb",0b100>, PredNewRel; let CextOpcode = "MUX", InputType = "reg", hasNewValue = 1 in @@ -434,7 +435,7 @@ def AND_ri : ALU32_ri<(outs IntRegs:$dst), s10ExtPred:$src2))]>, ImmRegRel; // Nop. -let hasSideEffects = 0 in +let hasSideEffects = 0, isCodeGenOnly = 0 in def A2_nop: ALU32Inst <(outs), (ins), "nop" > { let IClass = 0b0111; let Inst{27-24} = 0b1111; @@ -676,7 +677,7 @@ class T_ALU32_3op_cmp<string mnemonic, bits<2> MinOp, bit IsNeg, bit IsComm> let Inst{1-0} = Pd; } -let Itinerary = ALU32_3op_tc_2early_SLOT0123 in { +let Itinerary = ALU32_3op_tc_2early_SLOT0123, isCodeGenOnly = 0 in { def C2_cmpeq : T_ALU32_3op_cmp< "cmp.eq", 0b00, 0, 1>; def C2_cmpgt : T_ALU32_3op_cmp< "cmp.gt", 0b10, 0, 0>; def C2_cmpgtu : T_ALU32_3op_cmp< "cmp.gtu", 0b11, 0, 0>; |
