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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-18 17:09:41 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-05-18 17:09:41 +0000 |
| commit | 007b50fd35d1fb3f77a8a9bd6ca64e6dc38bafc8 (patch) | |
| tree | 769fff869651a4172bedfe1862a1c9db5800baeb /llvm/lib | |
| parent | b55009086931aa3c85fe3313dcfe005895d1f4ca (diff) | |
| download | bcm5719-llvm-007b50fd35d1fb3f77a8a9bd6ca64e6dc38bafc8.tar.gz bcm5719-llvm-007b50fd35d1fb3f77a8a9bd6ca64e6dc38bafc8.zip | |
[X86][BtVer2] Improve simulation of (V)PINSR values
Include the 6cy delay transferring from the GPR to FPU.
llvm-svn: 332737
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index 248939c464b..361ae95ce16 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -461,9 +461,10 @@ defm : JWriteResFpuPair<WriteVarVecShiftY,[JFPU01, JVALU], 1>; // NOTE: Doesn't // Vector insert/extract operations. //////////////////////////////////////////////////////////////////////////////// -defm : JWriteResFpuPair<WriteVecInsert, [JFPU01, JVALU], 1>; -def : WriteRes<WriteVecExtract, [JFPU0, JFPA, JALU0]> { let Latency = 3; } -def : WriteRes<WriteVecExtractSt, [JFPU1, JSTC, JSAGU]> { let Latency = 3; } +defm : X86WriteRes<WriteVecInsert, [JFPU01, JVALU], 7, [1,1], 2>; +defm : X86WriteRes<WriteVecInsertLd, [JFPU01, JVALU, JLAGU], 4, [1,1,1], 1>; +defm : X86WriteRes<WriteVecExtract, [JFPU0, JFPA, JALU0], 3, [1,1,1], 1>; +defm : X86WriteRes<WriteVecExtractSt, [JFPU1, JSTC, JSAGU], 3, [1,1,1], 1>; //////////////////////////////////////////////////////////////////////////////// // SSE42 String instructions. |
