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authorDaniel Dunbar <daniel@zuster.org>2009-07-29 00:02:19 +0000
committerDaniel Dunbar <daniel@zuster.org>2009-07-29 00:02:19 +0000
commit0033199c5015754e333dfd18a1b77d6f79c8cbe0 (patch)
tree6566ef7372337e467ee0e0a0553403bd86253803 /llvm/lib
parent8ae4e24c674f693b2d39087ce5abc38a01c5472c (diff)
downloadbcm5719-llvm-0033199c5015754e333dfd18a1b77d6f79c8cbe0.tar.gz
bcm5719-llvm-0033199c5015754e333dfd18a1b77d6f79c8cbe0.zip
Match X86 register names to number.
llvm-svn: 77404
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp22
-rw-r--r--llvm/lib/Target/X86/X86.td9
2 files changed, 27 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 12e9f937fc2..f172c1d22aa 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -42,6 +42,13 @@ private:
bool ParseOperand(X86Operand &Op);
bool ParseMemOperand(X86Operand &Op);
+
+ /// @name Auto-generated Match Functions
+ /// {
+
+ bool MatchRegisterName(const StringRef &Name, unsigned &RegNo);
+
+ /// }
public:
X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
@@ -118,10 +125,17 @@ struct X86Operand {
//
bool X86ATTAsmParser::ParseRegister(X86Operand &Op) {
- assert(getLexer().is(AsmToken::Register) && "Invalid token kind!");
+ AsmToken Tok = getLexer().getTok();
+ assert(Tok.is(AsmToken::Register) && "Invalid token kind!");
- // FIXME: Decode register number.
- Op = X86Operand::CreateReg(123);
+ // FIXME: Validate register for the current architecture; we have to do
+ // validation later, so maybe there is no need for this here.
+ unsigned RegNo;
+ assert(Tok.getString().startswith("%") && "Invalid register name!");
+ if (MatchRegisterName(Tok.getString().substr(1), RegNo))
+ return Error(Tok.getLoc(), "invalid register name");
+
+ Op = X86Operand::CreateReg(RegNo);
getLexer().Lex(); // Eat register token.
return false;
@@ -308,3 +322,5 @@ extern "C" void LLVMInitializeX86AsmParser() {
RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
}
+
+#include "X86GenAsmMatcher.inc"
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 47861d5a67d..effbddc8501 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -178,6 +178,12 @@ include "X86CallingConv.td"
// Assembly Printers
//===----------------------------------------------------------------------===//
+// Currently the X86 assembly parser only supports ATT syntax.
+def ATTAsmParser : AsmParser {
+ string AsmParserClassName = "ATTAsmParser";
+ int Variant = 0;
+}
+
// The X86 target supports two different syntaxes for emitting machine code.
// This is controlled by the -x86-asm-syntax={att|intel}
def ATTAsmWriter : AsmWriter {
@@ -189,10 +195,11 @@ def IntelAsmWriter : AsmWriter {
int Variant = 1;
}
-
def X86 : Target {
// Information about the instructions...
let InstructionSet = X86InstrInfo;
+ let AssemblyParsers = [ATTAsmParser];
+
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
}
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