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authorReid Spencer <rspencer@reidspencer.com>2006-11-08 06:47:33 +0000
committerReid Spencer <rspencer@reidspencer.com>2006-11-08 06:47:33 +0000
commitfdff938a7e4988da80be038acb1c6717d61b531a (patch)
tree2270b132b8a1fe22f63b56653ebf71dac480ad84 /llvm/lib/VMCore/Instruction.cpp
parent41f6c7cfb24169288c69d0dc5abf5518c142b76e (diff)
downloadbcm5719-llvm-fdff938a7e4988da80be038acb1c6717d61b531a.tar.gz
bcm5719-llvm-fdff938a7e4988da80be038acb1c6717d61b531a.zip
For PR950:
This patch converts the old SHR instruction into two instructions, AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not dependent on the sign of their operands. llvm-svn: 31542
Diffstat (limited to 'llvm/lib/VMCore/Instruction.cpp')
-rw-r--r--llvm/lib/VMCore/Instruction.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/VMCore/Instruction.cpp b/llvm/lib/VMCore/Instruction.cpp
index 355c508b6a6..70b375902dc 100644
--- a/llvm/lib/VMCore/Instruction.cpp
+++ b/llvm/lib/VMCore/Instruction.cpp
@@ -128,7 +128,8 @@ const char *Instruction::getOpcodeName(unsigned OpCode) {
case Select: return "select";
case Call: return "call";
case Shl: return "shl";
- case Shr: return "shr";
+ case LShr: return "lshr";
+ case AShr: return "ashr";
case VAArg: return "va_arg";
case ExtractElement: return "extractelement";
case InsertElement: return "insertelement";
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