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authorDevang Patel <dpatel@apple.com>2008-03-04 22:05:14 +0000
committerDevang Patel <dpatel@apple.com>2008-03-04 22:05:14 +0000
commitce556d908bb4273a2c8a4382edc1463db439d714 (patch)
tree7e42d4a68c125034a6fa52d9f375ace5045a6db7 /llvm/lib/VMCore/AsmWriter.cpp
parent7aedc47285c03e2ca9032cfac257fba1f3da20b7 (diff)
downloadbcm5719-llvm-ce556d908bb4273a2c8a4382edc1463db439d714.tar.gz
bcm5719-llvm-ce556d908bb4273a2c8a4382edc1463db439d714.zip
Print types for all ret operands.
llvm-svn: 47911
Diffstat (limited to 'llvm/lib/VMCore/AsmWriter.cpp')
-rw-r--r--llvm/lib/VMCore/AsmWriter.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/VMCore/AsmWriter.cpp b/llvm/lib/VMCore/AsmWriter.cpp
index 595f478c72a..64119eddc82 100644
--- a/llvm/lib/VMCore/AsmWriter.cpp
+++ b/llvm/lib/VMCore/AsmWriter.cpp
@@ -1417,7 +1417,8 @@ void AssemblyWriter::printInstruction(const Instruction &I) {
const Type *TheType = Operand->getType();
// Select, Store and ShuffleVector always print all types.
- if (isa<SelectInst>(I) || isa<StoreInst>(I) || isa<ShuffleVectorInst>(I)) {
+ if (isa<SelectInst>(I) || isa<StoreInst>(I) || isa<ShuffleVectorInst>(I)
+ || isa<ReturnInst>(I)) {
PrintAllTypes = true;
} else {
for (unsigned i = 1, E = I.getNumOperands(); i != E; ++i) {
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