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| author | Zhou Sheng <zhousheng00@gmail.com> | 2008-06-05 14:23:44 +0000 |
|---|---|---|
| committer | Zhou Sheng <zhousheng00@gmail.com> | 2008-06-05 14:23:44 +0000 |
| commit | fbe1dc240cfb992153239062f0ae3ca3b29dad32 (patch) | |
| tree | 7aecb523ab8b4cdbaf607d9491266dcadc9cc5dd /llvm/lib/Transforms | |
| parent | 5eef32ba94532ad2bf3e80af1a7518c84dfb72d8 (diff) | |
| download | bcm5719-llvm-fbe1dc240cfb992153239062f0ae3ca3b29dad32.tar.gz bcm5719-llvm-fbe1dc240cfb992153239062f0ae3ca3b29dad32.zip | |
If BitWidth equals to ShtAmt, the RHSKnownZero[BitWidth-ShiftAmt-1] will
crash the opt. Just fix this.
Test case in llvm/test/Transforms/InstCombine/2008-06-05-ashr-crash.ll
llvm-svn: 52003
Diffstat (limited to 'llvm/lib/Transforms')
| -rw-r--r-- | llvm/lib/Transforms/Scalar/InstructionCombining.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp index 516841a7639..05e12692f4c 100644 --- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp @@ -1236,7 +1236,7 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, // If the input sign bit is known to be zero, or if none of the top bits // are demanded, turn this into an unsigned shift right. - if (RHSKnownZero[BitWidth-ShiftAmt-1] || + if (BitWidth == ShiftAmt || RHSKnownZero[BitWidth-ShiftAmt-1] || (HighBits & ~DemandedMask) == HighBits) { // Perform the logical shift right. Value *NewVal = BinaryOperator::CreateLShr( |
