diff options
| author | Zhou Sheng <zhousheng00@gmail.com> | 2007-03-14 09:07:33 +0000 |
|---|---|---|
| committer | Zhou Sheng <zhousheng00@gmail.com> | 2007-03-14 09:07:33 +0000 |
| commit | d8c645b0ba9ea18be617247f61b5a85898362f7b (patch) | |
| tree | 2fa03361cbc9e8be846dc44d6acd54a688d6480a /llvm/lib/Transforms | |
| parent | b9128445547544408b483e19a6da67b5e2dd4de6 (diff) | |
| download | bcm5719-llvm-d8c645b0ba9ea18be617247f61b5a85898362f7b.tar.gz bcm5719-llvm-d8c645b0ba9ea18be617247f61b5a85898362f7b.zip | |
ShiftAmt might equal to zero. Handle this situation.
llvm-svn: 35094
Diffstat (limited to 'llvm/lib/Transforms')
| -rw-r--r-- | llvm/lib/Transforms/Scalar/InstructionCombining.cpp | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp index e072d966a7b..1e5b7ec3ca2 100644 --- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp +++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp @@ -1997,7 +1997,8 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, RHSKnownZero <<= ShiftAmt; RHSKnownOne <<= ShiftAmt; // low bits known zero. - RHSKnownZero |= APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth); + if (ShiftAmt) + RHSKnownZero |= APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth); } break; case Instruction::LShr: @@ -2013,14 +2014,16 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, return true; assert((RHSKnownZero & RHSKnownOne) == 0 && "Bits known to be one AND zero?"); - // Compute the new bits that are at the top now. - APInt HighBits(APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth).shl( - BitWidth - ShiftAmt)); RHSKnownZero &= TypeMask; RHSKnownOne &= TypeMask; RHSKnownZero = APIntOps::lshr(RHSKnownZero, ShiftAmt); RHSKnownOne = APIntOps::lshr(RHSKnownOne, ShiftAmt); - RHSKnownZero |= HighBits; // high bits known zero. + if (ShiftAmt) { + // Compute the new bits that are at the top now. + APInt HighBits(APInt::getAllOnesValue(BitWidth).shl( + BitWidth - ShiftAmt)); + RHSKnownZero |= HighBits; // high bits known zero. + } } break; case Instruction::AShr: @@ -2048,8 +2051,7 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask, assert((RHSKnownZero & RHSKnownOne) == 0 && "Bits known to be one AND zero?"); // Compute the new bits that are at the top now. - APInt HighBits(APInt::getAllOnesValue(ShiftAmt).zextOrCopy(BitWidth).shl( - BitWidth - ShiftAmt)); + APInt HighBits(APInt::getAllOnesValue(BitWidth).shl(BitWidth - ShiftAmt)); RHSKnownZero &= TypeMask; RHSKnownOne &= TypeMask; RHSKnownZero = APIntOps::lshr(RHSKnownZero, ShiftAmt); |
