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authorLauro Ramos Venancio <lauro.venancio@gmail.com>2007-06-06 17:08:48 +0000
committerLauro Ramos Venancio <lauro.venancio@gmail.com>2007-06-06 17:08:48 +0000
commit368e8872db0e105a4cb62464bb13b6de6e9b193d (patch)
treed6123968c30a28de570b78685b8da34fc96b2b6c /llvm/lib/Transforms
parentcfb6f40424d2cb885aff818bdd7ef2a723fccedb (diff)
downloadbcm5719-llvm-368e8872db0e105a4cb62464bb13b6de6e9b193d.tar.gz
bcm5719-llvm-368e8872db0e105a4cb62464bb13b6de6e9b193d.zip
Fix PR1499.
llvm-svn: 37472
Diffstat (limited to 'llvm/lib/Transforms')
-rw-r--r--llvm/lib/Transforms/Scalar/InstructionCombining.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp
index 2a227423b60..01fcfabeba4 100644
--- a/llvm/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -1346,6 +1346,10 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
// Signed shift right.
APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
+ // If any of the "high bits" are demanded, we should set the sign bit as
+ // demanded.
+ if (DemandedMask.countLeadingZeros() <= ShiftAmt)
+ DemandedMaskIn.set(BitWidth-1);
if (SimplifyDemandedBits(I->getOperand(0),
DemandedMaskIn,
RHSKnownZero, RHSKnownOne, Depth+1))
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