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author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-04-19 19:44:45 +0000 |
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committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-04-19 19:44:45 +0000 |
commit | 1d9de10130ffd5444a5cc41a27467da5e25d3f51 (patch) | |
tree | 41619e2e3a43b964a7b7fa9fd5254830bd9002eb /llvm/lib/Transforms | |
parent | e885d5e4d3fffc40173a8d0c82a6d30b2400bdec (diff) | |
download | bcm5719-llvm-1d9de10130ffd5444a5cc41a27467da5e25d3f51.tar.gz bcm5719-llvm-1d9de10130ffd5444a5cc41a27467da5e25d3f51.zip |
[ARM NEON] Define vfms_f32 on ARM, and all vfms using vfma.
r259537 added vfma/vfms to armv7, but the builtin was only lowered
on the AArch64 side. Instead of supporting it on ARM, get rid of it.
The vfms builtin lowered to:
%nb = fsub float -0.0, %b
%r = @llvm.fma.f32(%a, %nb, %c)
Instead, define the operation in terms of vfma, and swap the
multiplicands. It now lowers to:
%na = fsub float -0.0, %a
%r = @llvm.fma.f32(%na, %b, %c)
This matches the instruction more closely, and lets current LLVM
generate the "natural" operand ordering:
fmls.2s v0, v1, v2
instead of the crooked (but equivalent):
fmls.2s v0, v2, v1
Except for theses changes, assembly is identical.
LLVM accepts both commutations, and the LLVM tests in:
test/CodeGen/AArch64/arm64-fmadd.ll
test/CodeGen/AArch64/fp-dp3.ll
test/CodeGen/AArch64/neon-fma.ll
test/CodeGen/ARM/fusedMAC.ll
already check either the new one only, or both.
Also verified against the test-suite unittests.
llvm-svn: 266807
Diffstat (limited to 'llvm/lib/Transforms')
0 files changed, 0 insertions, 0 deletions