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| author | Clement Courbet <courbet@google.com> | 2018-06-13 09:41:49 +0000 |
|---|---|---|
| committer | Clement Courbet <courbet@google.com> | 2018-06-13 09:41:49 +0000 |
| commit | 5eeed77f87c4e63a80c42da66d635537f72e5d11 (patch) | |
| tree | 99c82b12c7e0d73832f2bb75688adf3831322256 /llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | |
| parent | b10ef47a68c64e865b02ba6e2eb4e0b7d53caf0c (diff) | |
| download | bcm5719-llvm-5eeed77f87c4e63a80c42da66d635537f72e5d11.tar.gz bcm5719-llvm-5eeed77f87c4e63a80c42da66d635537f72e5d11.zip | |
[TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
Summary:
For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files.
For more obvious cases, I've ventured a fix.
Some notes:
- Exynos is especially fishy.
- AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice.
- The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit.
Also see PR37310.
Reviewers: RKSimon, craig.topper, javed.absar
Subscribers: kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D46356
llvm-svn: 334586
Diffstat (limited to 'llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp')
0 files changed, 0 insertions, 0 deletions
