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| author | Oliver Stannard <oliver.stannard@arm.com> | 2018-02-12 14:22:03 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-02-12 14:22:03 +0000 |
| commit | 426991730495a6666a7ff8d085d40e3b8626ca3b (patch) | |
| tree | 570b39e3beabf8b51f74358e328f1ed6ffaf4eab /llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | |
| parent | 39059d26306ae7b926eac66d4f90bcc999952b9a (diff) | |
| download | bcm5719-llvm-426991730495a6666a7ff8d085d40e3b8626ca3b.tar.gz bcm5719-llvm-426991730495a6666a7ff8d085d40e3b8626ca3b.zip | |
[AArch64] Improve v8.1-A code-gen for atomic load-subtract
Armv8.1-A added an atomic load-add instruction, but not a load-subtract
instruction. Our current code-generation for atomic load-subtract always
inserts a NEG instruction to negate it's argument, even if it could be
folded into a constant or another instruction.
This adds lowering early in selection DAG to convert a load-subtract
operation into a subtract and a load-add, allowing the normal DAG
optimisations to work on it.
I've left the old tablegen patterns in because they are still needed for
global isel.
Some of the tests in this patch are copied from D35375 by Chad Rosier (which
was abandoned).
Differential revision: https://reviews.llvm.org/D42477
llvm-svn: 324892
Diffstat (limited to 'llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp')
0 files changed, 0 insertions, 0 deletions
