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| author | Daniil Fukalov <daniil.fukalov@amd.com> | 2018-06-08 16:29:04 +0000 |
|---|---|---|
| committer | Daniil Fukalov <daniil.fukalov@amd.com> | 2018-06-08 16:29:04 +0000 |
| commit | c9a098b314ecb206f439aa70a893c1620fb2e96b (patch) | |
| tree | 816478d0b524bf8a63e190f5f12cf64fad757731 /llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | |
| parent | 37433dc2e143ddface44d01611b5a82455874b99 (diff) | |
| download | bcm5719-llvm-c9a098b314ecb206f439aa70a893c1620fb2e96b.tar.gz bcm5719-llvm-c9a098b314ecb206f439aa70a893c1620fb2e96b.zip | |
[AMDGPU] Inline asm - added i16, half and i128 types support
AMDGPU inline assembler support i16, half and i128 typed variables in constraints, but they were reported as error.
Needed to fix https://github.com/RadeonOpenCompute/ROCm/issues/341,
e.g. to be able to load with global_load_dwordx4 to a 128bit integer variable
Differential Revision: https://reviews.llvm.org/D44920
llvm-svn: 334301
Diffstat (limited to 'llvm/lib/Transforms/Vectorize/LoopVectorize.cpp')
0 files changed, 0 insertions, 0 deletions
