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| author | Heejin Ahn <aheejin@gmail.com> | 2018-07-24 21:06:44 +0000 |
|---|---|---|
| committer | Heejin Ahn <aheejin@gmail.com> | 2018-07-24 21:06:44 +0000 |
| commit | 8daef0751d4a881ce6d07aefb4d7120416f8f954 (patch) | |
| tree | f0e33372cd88bf44d9548b3fe72c662a9124eb2a /llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | |
| parent | 8db0befc6d34c6db33ce8210faccdb5da6c2f670 (diff) | |
| download | bcm5719-llvm-8daef0751d4a881ce6d07aefb4d7120416f8f954.tar.gz bcm5719-llvm-8daef0751d4a881ce6d07aefb4d7120416f8f954.zip | |
[WebAssembly] Add tests for weaker memory consistency orderings
Summary:
Currently all wasm atomic memory access instructions are sequentially
consistent, so even if LLVM IR specifies weaker orderings than that, we
should upgrade them to sequential ordering and treat them in the same
way.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49194
llvm-svn: 337854
Diffstat (limited to 'llvm/lib/Transforms/Vectorize/LoopVectorize.cpp')
0 files changed, 0 insertions, 0 deletions
