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author | Marek Olsak <marek.olsak@amd.com> | 2015-02-03 17:38:12 +0000 |
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committer | Marek Olsak <marek.olsak@amd.com> | 2015-02-03 17:38:12 +0000 |
commit | 191507e0b730e95321d2b4126e8a0220e013bdcd (patch) | |
tree | ffe61d5f7391b694de65af81a160a844cc7be19d /llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | |
parent | 7585a29bd426bdcfc90e6cbc64abb871273ca389 (diff) | |
download | bcm5719-llvm-191507e0b730e95321d2b4126e8a0220e013bdcd.tar.gz bcm5719-llvm-191507e0b730e95321d2b4126e8a0220e013bdcd.zip |
R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
This can happen when a REV instruction is commuted.
The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
(very useful to catch bugs where an unsupported instruction somehow makes
it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
to prevent REV from commuting to non-REV on VI
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 227990
Diffstat (limited to 'llvm/lib/Transforms/Vectorize/LoopVectorize.cpp')
0 files changed, 0 insertions, 0 deletions