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authorStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2017-01-18 17:30:05 +0000
committerStanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>2017-01-18 17:30:05 +0000
commita4e63ead4b43b0f6be70744b553a2dcb9bdbf605 (patch)
tree5777be033c6fa5da4fe016b0fe5cb9fd3bcf4275 /llvm/lib/Transforms/Utils/LoopVersioning.cpp
parentfde01046498b67510357bd9897dd68bfb3e8b110 (diff)
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[AMDGPU] Do not allow register coalescer to create big superregs
Limit register coalescer by not allowing it to artificially increase size of registers beyond dword. Such super-registers are in fact register sequences and not distinct HW registers. With more super-regs we would need to allocate adjacent registers and constraint regalloc more than needed. Moreover, our super registers are overlapping. For instance we have VGPR0_VGPR1_VGPR2, VGPR1_VGPR2_VGPR3, VGPR2_VGPR3_VGPR4 etc, which complicates registers allocation even more, resulting in excessive spilling. Differential Revision: https://reviews.llvm.org/D28782 llvm-svn: 292413
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopVersioning.cpp')
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