diff options
| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-01-18 17:30:05 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-01-18 17:30:05 +0000 |
| commit | a4e63ead4b43b0f6be70744b553a2dcb9bdbf605 (patch) | |
| tree | 5777be033c6fa5da4fe016b0fe5cb9fd3bcf4275 /llvm/lib/Transforms/Utils/LoopVersioning.cpp | |
| parent | fde01046498b67510357bd9897dd68bfb3e8b110 (diff) | |
| download | bcm5719-llvm-a4e63ead4b43b0f6be70744b553a2dcb9bdbf605.tar.gz bcm5719-llvm-a4e63ead4b43b0f6be70744b553a2dcb9bdbf605.zip | |
[AMDGPU] Do not allow register coalescer to create big superregs
Limit register coalescer by not allowing it to artificially increase
size of registers beyond dword. Such super-registers are in fact
register sequences and not distinct HW registers.
With more super-regs we would need to allocate adjacent registers
and constraint regalloc more than needed. Moreover, our super
registers are overlapping. For instance we have VGPR0_VGPR1_VGPR2,
VGPR1_VGPR2_VGPR3, VGPR2_VGPR3_VGPR4 etc, which complicates registers
allocation even more, resulting in excessive spilling.
Differential Revision: https://reviews.llvm.org/D28782
llvm-svn: 292413
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopVersioning.cpp')
0 files changed, 0 insertions, 0 deletions

