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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 17:08:36 +0000 |
|---|---|---|
| committer | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2013-05-31 17:08:36 +0000 |
| commit | f1ed334d552a5e1dc608cdff4ad9319acac76520 (patch) | |
| tree | a6ace57d7ad51583a4a4976656d14e789d5b0621 /llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | |
| parent | 4d5bae167976f5b66443f991e5975a53d8e47bc7 (diff) | |
| download | bcm5719-llvm-f1ed334d552a5e1dc608cdff4ad9319acac76520.tar.gz bcm5719-llvm-f1ed334d552a5e1dc608cdff4ad9319acac76520.zip | |
Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.
In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.
llvm-svn: 183020
Diffstat (limited to 'llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp')
0 files changed, 0 insertions, 0 deletions
