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| author | Ehsan Amiri <amehsan@ca.ibm.com> | 2016-10-24 15:46:58 +0000 |
|---|---|---|
| committer | Ehsan Amiri <amehsan@ca.ibm.com> | 2016-10-24 15:46:58 +0000 |
| commit | 1f31e9157de78e07e39a62bddefe9a137fee0216 (patch) | |
| tree | f3e59fa74f8ef42ccd60f8d889725d8ac6c52229 /llvm/lib/Transforms/Scalar/EarlyCSE.cpp | |
| parent | 7b12e367406347ac22716b97198581a86dee7152 (diff) | |
| download | bcm5719-llvm-1f31e9157de78e07e39a62bddefe9a137fee0216.tar.gz bcm5719-llvm-1f31e9157de78e07e39a62bddefe9a137fee0216.zip | |
[PPC] Better codegen for AND, ANY_EXT, SRL sequence
https://reviews.llvm.org/D24924
This improves the code generated for a sequence of AND, ANY_EXT, SRL instructions. This is a targetted fix for this special pattern. The pattern is generated by target independet dag combiner and so a more general fix may not be necessary. If we come across other similar cases, some ideas for handling it are discussed on the code review.
llvm-svn: 284983
Diffstat (limited to 'llvm/lib/Transforms/Scalar/EarlyCSE.cpp')
0 files changed, 0 insertions, 0 deletions
