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| author | Momchil Velikov <momchil.velikov@arm.com> | 2018-01-26 10:20:58 +0000 |
|---|---|---|
| committer | Momchil Velikov <momchil.velikov@arm.com> | 2018-01-26 10:20:58 +0000 |
| commit | d2cc6fd90b7d72ff0bd5705ff57c6d0980c345ba (patch) | |
| tree | 67229e3f798897e1bf4cd9a068d3e2f17e7ca6fd /llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp | |
| parent | cbc5a688f3f247c989d6dd21c87e7281a83dff12 (diff) | |
| download | bcm5719-llvm-d2cc6fd90b7d72ff0bd5705ff57c6d0980c345ba.tar.gz bcm5719-llvm-d2cc6fd90b7d72ff0bd5705ff57c6d0980c345ba.zip | |
[ARM] Accept a subset of Thumb GPR register class when emitting an SP-relative
load instruction
The function `Thumb1InstrInfo::loadRegFromStackSlot` accepts only the `tGPR`
register class. The function serves to emit a `tLDRspi` instruction and
certainly any subset of the `tGPR` register class is a valid destination of the
load.
Differential revision: https://reviews.llvm.org/D42535
llvm-svn: 323514
Diffstat (limited to 'llvm/lib/Transforms/Scalar/CallSiteSplitting.cpp')
0 files changed, 0 insertions, 0 deletions
