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author | Tom Stellard <tstellar@redhat.com> | 2018-05-03 21:44:16 +0000 |
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committer | Tom Stellard <tstellar@redhat.com> | 2018-05-03 21:44:16 +0000 |
commit | abc9871d6099d154dcab127b3676f015f76accec (patch) | |
tree | 71b754fb3b8016075247dc4d985d527d0373acef /llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | |
parent | 6e713d9866daf42a2cec19eb26bf5ea0d77ec3e0 (diff) | |
download | bcm5719-llvm-abc9871d6099d154dcab127b3676f015f76accec.tar.gz bcm5719-llvm-abc9871d6099d154dcab127b3676f015f76accec.zip |
GlobalISel: Use a callback to compute constrained reg class for unallocatble registers
Summary:
constrainOperandRegClass() currently fails if it tries to constrain the
register class of an operand that is defeined with an unallocatable register
class. This patch resolves this by adding a target callback to compute
register constriants in this case.
This is required by the AMDGPU because many of its instructions have source opreands
defined with the unallocatable register classe VS_32 which is a union of two allocatable
register classes VGPR_32 and SReg_32.
Reviewers: dsanders, aditya_nandakumar
Reviewed By: aditya_nandakumar
Subscribers: rovka, kristof.beyls, tpr, llvm-commits
Differential Revision: https://reviews.llvm.org/D45991
llvm-svn: 331485
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp')
0 files changed, 0 insertions, 0 deletions