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| author | Sanjay Patel <spatel@rotateright.com> | 2016-11-22 22:05:48 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-11-22 22:05:48 +0000 |
| commit | e359eaaf708e227eeeaf3f4a9640e5cde0f3c05a (patch) | |
| tree | 47bd8a4315d352018517d37c89c2e9dd60e6d22e /llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp | |
| parent | eda365cf807c22ad939dd6d3017cf6a3679675b6 (diff) | |
| download | bcm5719-llvm-e359eaaf708e227eeeaf3f4a9640e5cde0f3c05a.tar.gz bcm5719-llvm-e359eaaf708e227eeeaf3f4a9640e5cde0f3c05a.zip | |
[InstCombine] change bitwise logic type to eliminate bitcasts
In PR27925:
https://llvm.org/bugs/show_bug.cgi?id=27925
...we proposed adding this fold to eliminate a bitcast. In D20774, there was
some concern about changing the type of a bitwise op as well as creating
bitcasts that might not be free for a target. However, if we're strictly
eliminating an instruction (by limiting this to one-use ops), then we should
be able to do this in InstCombine.
But we're cautiously restricting the transform for now to vector types to
avoid possible backend problems. A transform to make sure the logic op is
legal for the target should be added to reverse this transform and improve
codegen.
Differential Revision: https://reviews.llvm.org/D26641
llvm-svn: 287707
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp')
0 files changed, 0 insertions, 0 deletions
