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author | Sanjay Patel <spatel@rotateright.com> | 2018-11-13 23:27:23 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2018-11-13 23:27:23 +0000 |
commit | a139564896f2d0d4dc4dc491c4b17c9f01975a26 (patch) | |
tree | 2a2f2ba388d4044d1e62ab0c1f77bcd238b09e5c /llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp | |
parent | e0c00718ec2312ce55c79340a2c986a99e279cf9 (diff) | |
download | bcm5719-llvm-a139564896f2d0d4dc4dc491c4b17c9f01975a26.tar.gz bcm5719-llvm-a139564896f2d0d4dc4dc491c4b17c9f01975a26.zip |
[InstCombine] fold funnel shift amount based on demanded bits
The shift amount of a funnel shift is modulo the scalar bitwidth:
http://llvm.org/docs/LangRef.html#llvm-fshl-intrinsic
...so we can use demanded bits analysis on that operand to simplify it
when we have a power-of-2 bitwidth.
This is another step towards canonicalizing {shift/shift/or} to the
intrinsics in IR.
Differential Revision: https://reviews.llvm.org/D54478
llvm-svn: 346814
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp')
-rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index fae47ec93b9..a99eaf013e6 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -1990,6 +1990,20 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) { return I; break; + case Intrinsic::fshl: + case Intrinsic::fshr: { + // The shift amount (operand 2) of a funnel shift is modulo the bitwidth, + // so only the low bits of the shift amount are demanded if the bitwidth is + // a power-of-2. + unsigned BitWidth = II->getType()->getScalarSizeInBits(); + if (!isPowerOf2_32(BitWidth)) + break; + APInt Op2Demanded = APInt::getLowBitsSet(BitWidth, Log2_32_Ceil(BitWidth)); + KnownBits Op2Known(BitWidth); + if (SimplifyDemandedBits(II, 2, Op2Demanded, Op2Known)) + return &CI; + break; + } case Intrinsic::uadd_with_overflow: case Intrinsic::sadd_with_overflow: case Intrinsic::umul_with_overflow: |