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| author | Evandro Menezes <e.menezes@samsung.com> | 2018-11-23 21:17:33 +0000 |
|---|---|---|
| committer | Evandro Menezes <e.menezes@samsung.com> | 2018-11-23 21:17:33 +0000 |
| commit | 079bf4b7b4fc3c2ffeb57b02a580408cd7259bf8 (patch) | |
| tree | 791783e2de31fa55adc867101859895218b32553 /llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp | |
| parent | 7e32cc83533858716dae4b49b345338e08e695e8 (diff) | |
| download | bcm5719-llvm-079bf4b7b4fc3c2ffeb57b02a580408cd7259bf8.tar.gz bcm5719-llvm-079bf4b7b4fc3c2ffeb57b02a580408cd7259bf8.zip | |
[TableGen] Emit more variant transitions
`llvm-mca` relies on the predicates to be based on `MCSchedPredicate` in order
to resolve the scheduling for variant instructions. Otherwise, it aborts
the building of the instruction model early.
However, the scheduling model emitter in `TableGen` gives up too soon, unless
all processors use only such predicates.
In order to allow more processors to be used with `llvm-mca`, this patch
emits scheduling transitions if any processor uses these predicates. The
transition emitted for the processors using legacy predicates is the one
specified with `NoSchedPred`, which is based on `MCSchedPredicate`.
Preferably, `llvm-mca` should instead assume a reasonable default when a
variant transition is not based on `MCSchedPredicate` for a given processor.
This issue should be revisited in the future.
Differential revision: https://reviews.llvm.org/D54648
llvm-svn: 347504
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp')
0 files changed, 0 insertions, 0 deletions
