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authorPhilip Reames <listmail@philipreames.com>2019-02-15 21:31:39 +0000
committerPhilip Reames <listmail@philipreames.com>2019-02-15 21:31:39 +0000
commit8220ecbce1a42410f07f0f3ea546661f76a6b896 (patch)
tree9757584225b6d1ebefa80f5977603485c494cc22 /llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
parentcae6c767e886b587e3b6d698c186f75c941bb11d (diff)
downloadbcm5719-llvm-8220ecbce1a42410f07f0f3ea546661f76a6b896.tar.gz
bcm5719-llvm-8220ecbce1a42410f07f0f3ea546661f76a6b896.zip
[InstCombine] Address a couple stylistic issues pointed out by reviewer [NFC]
Better addressing comments from https://reviews.llvm.org/D58290. llvm-svn: 354171
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp')
-rw-r--r--llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
index 58da7eb6759..b857741e840 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
@@ -26,8 +26,7 @@ bool isIdempotentRMW(AtomicRMWInst& RMWI) {
// TODO: Handle fadd, fsub?
return false;
- AtomicRMWInst::BinOp Op = RMWI.getOperation();
- switch(Op) {
+ switch(RMWI.getOperation()) {
case AtomicRMWInst::Add:
case AtomicRMWInst::Sub:
case AtomicRMWInst::Or:
@@ -55,12 +54,12 @@ bool isSaturating(AtomicRMWInst& RMWI) {
if(!C)
return false;
- AtomicRMWInst::BinOp Op = RMWI.getOperation();
- switch(Op) {
+ switch(RMWI.getOperation()) {
default:
// TODO: fadd, fsub w/Nan
- // Note: We avoid listing xchg to prevent transform cycles.
return false;
+ case AtomicRMWInst::Xchg:
+ return true;
case AtomicRMWInst::Or:
return C->isAllOnesValue();
case AtomicRMWInst::And:
@@ -87,7 +86,8 @@ Instruction *InstCombiner::visitAtomicRMWInst(AtomicRMWInst &RMWI) {
// Any atomicrmw op which produces a known result in memory can be
// replaced w/an atomicrmw xchg.
- if (isSaturating(RMWI)) {
+ if (isSaturating(RMWI) &&
+ RMWI.getOperation() != AtomicRMWInst::Xchg) {
RMWI.setOperation(AtomicRMWInst::Xchg);
return &RMWI;
}
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