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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-03-21 18:02:18 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-03-21 18:02:18 +0000 |
| commit | cb38a6bd35b2ef94ef675ba1dccd00ad6bfac281 (patch) | |
| tree | 2e8699f3b9f2b087a13fb10d310531c4492b53a5 /llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | |
| parent | bd6a74e1facb648f2d4dd94ac0f1a62f6dc2b44b (diff) | |
| download | bcm5719-llvm-cb38a6bd35b2ef94ef675ba1dccd00ad6bfac281.tar.gz bcm5719-llvm-cb38a6bd35b2ef94ef675ba1dccd00ad6bfac281.zip | |
AMDGPU: Remove SignBitIsZero for mubuf scratch offsets
These instructions do not have the same negative base
address problem that DS instructions do on SI.
llvm-svn: 263964
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp')
0 files changed, 0 insertions, 0 deletions
