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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2018-10-03 15:02:44 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2018-10-03 15:02:44 +0000
commit207e0217f9a4bc1593c8851a62bd42852e78abe9 (patch)
treeeccf757bd9e9a3bb508b9b22d586c8c2b89d046d /llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
parent92d02027c26733410d5fbb8a10ebf7a3c745e4d8 (diff)
downloadbcm5719-llvm-207e0217f9a4bc1593c8851a62bd42852e78abe9.tar.gz
bcm5719-llvm-207e0217f9a4bc1593c8851a62bd42852e78abe9.zip
[llvm-mca] Add support for move elimination in class RegisterFile.
This patch teaches class RegisterFile how to analyze register writes from instructions that are move elimination candidates. In particular, it teaches it how to check if a move can be effectively eliminated by the underlying PRF, and (if necessary) how to perform move elimination. The long term goal is to allow processor models to describe instructions that are valid move elimination candidates. The idea is to let register file definitions in tablegen declare if/when moves can be eliminated. This patch is a non functional change. The logic that performs move elimination is currently disabled. A future patch will add support for move elimination in the processor models, and enable this new code path. llvm-svn: 343691
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