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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-01-31 10:18:29 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-01-31 10:18:29 +0000 |
| commit | 98d5359ea2a07ebeaf6eb9dbc7c80fb4fbd72885 (patch) | |
| tree | f2fd93c032eba5a12fd8f4092a9ed7bd4ce1a26a /llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp | |
| parent | c2091808280a054cf9cdb7897335a5039c3a9cf8 (diff) | |
| download | bcm5719-llvm-98d5359ea2a07ebeaf6eb9dbc7c80fb4fbd72885.tar.gz bcm5719-llvm-98d5359ea2a07ebeaf6eb9dbc7c80fb4fbd72885.zip | |
[ARM] Armv8.2-A FP16 code generation (part 2/3)
Half-precision arguments and return values are passed as if it were an int or
float for ARM. This results in truncates and bitcasts to/from i16 and f16
values, which are legalized very early to stack stores/loads. When FullFP16 is
enabled, we want to avoid codegen for these bitcasts as it is unnecessary and
inefficient.
Differential Revision: https://reviews.llvm.org/D42580
llvm-svn: 323861
Diffstat (limited to 'llvm/lib/Transforms/AggressiveInstCombine/TruncInstCombine.cpp')
0 files changed, 0 insertions, 0 deletions
