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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 07:27:53 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2017-12-15 07:27:53 +0000 |
| commit | 6995e5dae78d20c7e04ef5cdc259ee5cc1eb4e57 (patch) | |
| tree | 66d8147a1b333df5f115fda9b09149f32f7be763 /llvm/lib/Testing | |
| parent | 7cfacbf6ea8222b61742e9734506432c59da21f4 (diff) | |
| download | bcm5719-llvm-6995e5dae78d20c7e04ef5cdc259ee5cc1eb4e57.tar.gz bcm5719-llvm-6995e5dae78d20c7e04ef5cdc259ee5cc1eb4e57.zip | |
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
This patch adds the necessary infrastructure to convert instructions that
take two register operands to those that take a register and immediate if
the necessary operand is produced by a load-immediate. Furthermore, it uses
this infrastructure to perform such conversions twice - first at MachineSSA
and then pre-emit.
There are a number of reasons we may end up with opportunities for this
transformation, including but not limited to:
- X-Form instructions chosen since the exact offset isn't available at ISEL time
- Atomic instructions with constant operands (we will add patterns for this
in the future)
- Tail duplication may duplicate code where one block contains this redundancy
- When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant
comparands specially
Furthermore, this patch moves the initialization of PPCMIPeepholePass so that
it can be used for MIR tests.
llvm-svn: 320791
Diffstat (limited to 'llvm/lib/Testing')
0 files changed, 0 insertions, 0 deletions
