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authorRafael Espindola <rafael.espindola@gmail.com>2014-11-10 18:11:10 +0000
committerRafael Espindola <rafael.espindola@gmail.com>2014-11-10 18:11:10 +0000
commit4aa6bea7a2d79ddbb0023baaa7ce5009d1f6dfbd (patch)
tree62ea0ca2dbca372d6a5b2c2f3e134ead9085dd25 /llvm/lib/Target/XCore
parent94794d08b94a8329d3f833ef0d2ac01938dd9cce (diff)
downloadbcm5719-llvm-4aa6bea7a2d79ddbb0023baaa7ce5009d1f6dfbd.tar.gz
bcm5719-llvm-4aa6bea7a2d79ddbb0023baaa7ce5009d1f6dfbd.zip
Misc style fixes. NFC.
This fixes a few cases of: * Wrong variable name style. * Lines longer than 80 columns. * Repeated names in comments. * clang-format of the above. This make the next patch a lot easier to read. llvm-svn: 221615
Diffstat (limited to 'llvm/lib/Target/XCore')
-rw-r--r--llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp45
1 files changed, 18 insertions, 27 deletions
diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index b1d9ab82813..7ac0a55b68a 100644
--- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -36,44 +36,39 @@ public:
XCoreDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
MCDisassembler(STI, Ctx) {}
- /// \brief See MCDisassembler.
- DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
- const MemoryObject &region, uint64_t address,
- raw_ostream &vStream,
- raw_ostream &cStream) const override;
+ DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
+ const MemoryObject &Region, uint64_t Address,
+ raw_ostream &VStream,
+ raw_ostream &CStream) const override;
};
}
-static bool readInstruction16(const MemoryObject &region,
- uint64_t address,
- uint64_t &size,
- uint16_t &insn) {
+static bool readInstruction16(const MemoryObject &Region, uint64_t Address,
+ uint64_t &Size, uint16_t &Insn) {
uint8_t Bytes[4];
// We want to read exactly 2 Bytes of data.
- if (region.readBytes(address, 2, Bytes) == -1) {
- size = 0;
+ if (Region.readBytes(Address, 2, Bytes) == -1) {
+ Size = 0;
return false;
}
// Encoded as a little-endian 16-bit word in the stream.
- insn = (Bytes[0] << 0) | (Bytes[1] << 8);
+ Insn = (Bytes[0] << 0) | (Bytes[1] << 8);
return true;
}
-static bool readInstruction32(const MemoryObject &region,
- uint64_t address,
- uint64_t &size,
- uint32_t &insn) {
+static bool readInstruction32(const MemoryObject &Region, uint64_t Address,
+ uint64_t &Size, uint32_t &Insn) {
uint8_t Bytes[4];
// We want to read exactly 4 Bytes of data.
- if (region.readBytes(address, 4, Bytes) == -1) {
- size = 0;
+ if (Region.readBytes(Address, 4, Bytes) == -1) {
+ Size = 0;
return false;
}
// Encoded as a little-endian 32-bit word in the stream.
- insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
- (Bytes[3] << 24);
+ Insn =
+ (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24);
return true;
}
@@ -745,13 +740,9 @@ DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
-MCDisassembler::DecodeStatus
-XCoreDisassembler::getInstruction(MCInst &instr,
- uint64_t &Size,
- const MemoryObject &Region,
- uint64_t Address,
- raw_ostream &vStream,
- raw_ostream &cStream) const {
+MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(
+ MCInst &instr, uint64_t &Size, const MemoryObject &Region, uint64_t Address,
+ raw_ostream &vStream, raw_ostream &cStream) const {
uint16_t insn16;
if (!readInstruction16(Region, Address, Size, insn16)) {
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