diff options
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-14 20:43:16 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-09-14 20:43:16 +0000 |
| commit | 1b9fc8ed659589ee2f1d010adfd63f3d890c6ec3 (patch) | |
| tree | 27b082ad9831ad1d7dbddbd99b4c07e76e1db43e /llvm/lib/Target/XCore | |
| parent | 0ac172d8ede295c30946f6af2dafb68c7c7aa201 (diff) | |
| download | bcm5719-llvm-1b9fc8ed659589ee2f1d010adfd63f3d890c6ec3.tar.gz bcm5719-llvm-1b9fc8ed659589ee2f1d010adfd63f3d890c6ec3.zip | |
Finish renaming remaining analyzeBranch functions
llvm-svn: 281535
Diffstat (limited to 'llvm/lib/Target/XCore')
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreInstrInfo.h | 4 |
2 files changed, 6 insertions, 8 deletions
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index 1adcc19b9c7..7a9c6fc93f8 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -184,7 +184,7 @@ static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) /// operands can be passed to other TargetInstrInfo methods to create new /// branches. /// -/// Note that RemoveBranch and insertBranch must be implemented to support +/// Note that removeBranch and insertBranch must be implemented to support /// cases where this method returns success. /// bool XCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB, @@ -304,7 +304,7 @@ unsigned XCoreInstrInfo::insertBranch(MachineBasicBlock &MBB, } unsigned -XCoreInstrInfo::RemoveBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { +XCoreInstrInfo::removeBranch(MachineBasicBlock &MBB, int *BytesRemoved) const { assert(!BytesRemoved && "code size not handled"); MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); @@ -400,11 +400,9 @@ void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, .addMemOperand(MMO); } -/// ReverseBranchCondition - Return the inverse opcode of the -/// specified Branch instruction. bool XCoreInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { - assert((Cond.size() == 2) && +reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { + assert((Cond.size() == 2) && "Invalid XCore branch condition!"); Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); return false; diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index ce8c14f3e0a..a377784caf4 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -60,7 +60,7 @@ public: const DebugLoc &DL, int *BytesAdded = nullptr) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB, + unsigned removeBranch(MachineBasicBlock &MBB, int *BytesRemoved = nullptr) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, @@ -79,7 +79,7 @@ public: const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - bool ReverseBranchCondition( + bool reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const override; // Emit code before MBBI to load immediate value into physical register Reg. |
