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authorDan Gohman <gohman@apple.com>2010-07-09 00:39:23 +0000
committerDan Gohman <gohman@apple.com>2010-07-09 00:39:23 +0000
commit0b5aa1cdd3946745b54bb33902db391d41e53cd8 (patch)
treed505d885d7eb22b720c4bdc9ee3c18c8f707520e /llvm/lib/Target/XCore
parente6cc0d33bbb378784e6332e810e7c40f350ee1f7 (diff)
downloadbcm5719-llvm-0b5aa1cdd3946745b54bb33902db391d41e53cd8.tar.gz
bcm5719-llvm-0b5aa1cdd3946745b54bb33902db391d41e53cd8.zip
Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
Diffstat (limited to 'llvm/lib/Target/XCore')
-rw-r--r--llvm/lib/Target/XCore/XCoreISelLowering.cpp5
-rw-r--r--llvm/lib/Target/XCore/XCoreISelLowering.h3
2 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 6a25e06335e..abe7b2fd42b 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -1135,13 +1135,12 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
bool XCoreTargetLowering::
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<EVT> &OutTys,
- const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
+ const SmallVectorImpl<ISD::OutputArg> &Outs,
LLVMContext &Context) const {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
RVLocs, Context);
- return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
+ return CCInfo.CheckReturn(Outs, RetCC_XCore);
}
SDValue
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.h b/llvm/lib/Target/XCore/XCoreISelLowering.h
index 46643014a09..febc198f4fa 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.h
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.h
@@ -193,8 +193,7 @@ namespace llvm {
virtual bool
CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
- const SmallVectorImpl<EVT> &OutTys,
- const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
+ const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
LLVMContext &Context) const;
};
}
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