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| author | Craig Topper <craig.topper@gmail.com> | 2012-04-20 07:30:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-04-20 07:30:17 +0000 |
| commit | c7242e054ddba4ad0514cb632903bfa0aa1461f5 (patch) | |
| tree | 3a03dffc586235440d90d26866c104b586b30910 /llvm/lib/Target/XCore/XCoreISelLowering.cpp | |
| parent | 61e582f6bccfffdcd3ba93a5bf5a7e1c5b882a6d (diff) | |
| download | bcm5719-llvm-c7242e054ddba4ad0514cb632903bfa0aa1461f5.tar.gz bcm5719-llvm-c7242e054ddba4ad0514cb632903bfa0aa1461f5.zip | |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
llvm-svn: 155188
Diffstat (limited to 'llvm/lib/Target/XCore/XCoreISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/XCore/XCoreISelLowering.cpp | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp index fdf2b783241..ee4ba10912d 100644 --- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp +++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp @@ -66,7 +66,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) Subtarget(*XTM.getSubtargetImpl()) { // Set up the register classes. - addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); + addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); // Compute derived properties from the register classes computeRegisterProperties(); @@ -1121,8 +1121,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, llvm_unreachable(0); } case MVT::i32: - unsigned VReg = RegInfo.createVirtualRegister( - XCore::GRRegsRegisterClass); + unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } @@ -1172,8 +1171,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, offset -= StackSlotSize; SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); // Move argument from phys reg -> virt reg - unsigned VReg = RegInfo.createVirtualRegister( - XCore::GRRegsRegisterClass); + unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); RegInfo.addLiveIn(ArgRegs[i], VReg); SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); // Move argument from virt reg -> stack @@ -1611,7 +1609,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, switch (Constraint[0]) { default : break; case 'r': - return std::make_pair(0U, XCore::GRRegsRegisterClass); + return std::make_pair(0U, &XCore::GRRegsRegClass); } } // Use the default implementation in TargetLowering to convert the register |
