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authorChad Rosier <mcrosier@apple.com>2013-06-22 18:37:38 +0000
committerChad Rosier <mcrosier@apple.com>2013-06-22 18:37:38 +0000
commit295bd43adb9c514c53f6df861ae1c6e97c23a53a (patch)
treed13c5eb42f4e12a882379551c8263b927fed7cbe /llvm/lib/Target/XCore/XCoreISelLowering.cpp
parent40d7f354b5637066a7ad3d50e19df482ee234d53 (diff)
downloadbcm5719-llvm-295bd43adb9c514c53f6df861ae1c6e97c23a53a.tar.gz
bcm5719-llvm-295bd43adb9c514c53f6df861ae1c6e97c23a53a.zip
The getRegForInlineAsmConstraint function should only accept MVT value types.
llvm-svn: 184642
Diffstat (limited to 'llvm/lib/Target/XCore/XCoreISelLowering.cpp')
-rw-r--r--llvm/lib/Target/XCore/XCoreISelLowering.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/XCore/XCoreISelLowering.cpp b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
index 7b89b1a1d41..5af2c9c0cc3 100644
--- a/llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -1582,7 +1582,7 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
std::pair<unsigned, const TargetRegisterClass*>
XCoreTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
- EVT VT) const {
+ MVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
default : break;
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