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| author | Richard Osborne <richard@xmos.com> | 2013-01-25 21:25:12 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-25 21:25:12 +0000 |
| commit | a520a7dcf3c681b75373357c6fec65b4d4aa7440 (patch) | |
| tree | 3f0e1047c88df6175cc164f31672130228d4e88b /llvm/lib/Target/XCore/Disassembler | |
| parent | 9a228a13c64959359e072b92c17e16ed778c748e (diff) | |
| download | bcm5719-llvm-a520a7dcf3c681b75373357c6fec65b4d4aa7440.tar.gz bcm5719-llvm-a520a7dcf3c681b75373357c6fec65b4d4aa7440.zip | |
Use the correct format in the STW / SETPSC instruction names.
llvm-svn: 173494
Diffstat (limited to 'llvm/lib/Target/XCore/Disassembler')
| -rw-r--r-- | llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index e785030c387..821c33da516 100644 --- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -401,7 +401,7 @@ DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address, fieldFromInstruction(Insn, 27, 5) << 4; switch (Opcode) { case 0x0c: - Inst.setOpcode(XCore::STW_3r); + Inst.setOpcode(XCore::STW_l3r); return DecodeL3RInstruction(Inst, Insn, Address, Decoder); case 0x1c: Inst.setOpcode(XCore::XOR_l3r); |
