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| author | Richard Osborne <richard@xmos.com> | 2013-01-23 20:08:11 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-23 20:08:11 +0000 |
| commit | 54e311821f679ea12458824b2ac41ffdbae5c195 (patch) | |
| tree | cf1efa0956d8c13d81cfbed8aeac191834b6b637 /llvm/lib/Target/XCore/Disassembler | |
| parent | c0d3c4efe665ed51a09456e075be59fb7bf71cdb (diff) | |
| download | bcm5719-llvm-54e311821f679ea12458824b2ac41ffdbae5c195.tar.gz bcm5719-llvm-54e311821f679ea12458824b2ac41ffdbae5c195.zip | |
Add instruction encodings / disassembly support for l6r instructions.
llvm-svn: 173288
Diffstat (limited to 'llvm/lib/Target/XCore/Disassembler')
| -rw-r--r-- | llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index e6861bf0f3a..73aeb9c755e 100644 --- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -170,6 +170,11 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeL6RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -572,6 +577,26 @@ DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3, Op4, Op5, Op6; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S != MCDisassembler::Success) + return S; + S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); + if (S != MCDisassembler::Success) + return S; + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, |
