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authorRichard Osborne <richard@xmos.com>2013-05-05 13:20:22 +0000
committerRichard Osborne <richard@xmos.com>2013-05-05 13:20:22 +0000
commit53a04fe2b4b1ad508dc77774ffc3e0271c855632 (patch)
tree8956b7ac0c99063ac01e3b10978053548d657407 /llvm/lib/Target/XCore/Disassembler
parent1ce5d800665560456ab097b5cb9775794c05f39b (diff)
downloadbcm5719-llvm-53a04fe2b4b1ad508dc77774ffc3e0271c855632.tar.gz
bcm5719-llvm-53a04fe2b4b1ad508dc77774ffc3e0271c855632.zip
[XCore] Remove '-' from back branch asm syntax.
Instead operands are treated as negative immediates where the sign bit is implicit in the instruction encoding. llvm-svn: 181151
Diffstat (limited to 'llvm/lib/Target/XCore/Disassembler')
-rw-r--r--llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index 7282f2f1e5c..a2ae40c58a6 100644
--- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -97,6 +97,9 @@ static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
+
static DecodeStatus Decode2RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -239,6 +242,12 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder) {
+ Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus
Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
unsigned Combined = fieldFromInstruction(Insn, 6, 5);
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