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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-05 09:57:20 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-03-05 09:57:20 +0000 |
| commit | 9f5c251d574c766e08d332ee7f3cefb88bc72438 (patch) | |
| tree | 639925e45dd7230eae23fb350e5736bd218f949a /llvm/lib/Target/X86/X86WinAllocaExpander.cpp | |
| parent | 4bc8292a46f2618eca5b8a08b290c6a4f6418e93 (diff) | |
| download | bcm5719-llvm-9f5c251d574c766e08d332ee7f3cefb88bc72438.tar.gz bcm5719-llvm-9f5c251d574c766e08d332ee7f3cefb88bc72438.zip | |
[X86][SSE] Lower 128-bit vectors to SIGN/ZERO_EXTEND_VECTOR_IN_REG ops
As described on PR31712, we miss a variety of legalization combines because we lower these to X86ISD::VSEXT/VZEXT despite them having the same functionality. This patch makes 128-bit (SSE41) SIGN/ZERO_EXTEND_VECTOR_IN_REG ops legal, adds the necessary tablegen plumbing and uses a helper 'getExtendInVec' to decide when to use SIGN/ZERO_EXTEND_VECTOR_IN_REG or VSEXT/VZEXT.
We're missing a couple of shuffle combines that will be added in a future patch for review.
Later patches can then support the AVX2 cases as a mixture of SIGN/ZERO_EXTEND and SIGN/ZERO_EXTEND_VECTOR_IN_REG, and then finally deal with the AVX512 cases.
Differential Revision: https://reviews.llvm.org/D30549
llvm-svn: 296985
Diffstat (limited to 'llvm/lib/Target/X86/X86WinAllocaExpander.cpp')
0 files changed, 0 insertions, 0 deletions
