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author | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-01-05 10:46:09 +0000 |
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committer | Elena Demikhovsky <elena.demikhovsky@intel.com> | 2014-01-05 10:46:09 +0000 |
commit | 52e4a0e109dd0428b40ae3b380616cd211b3a705 (patch) | |
tree | 844a554f5be2a8f91b25bc37538dbe473d51e72e /llvm/lib/Target/X86/X86VZeroUpper.cpp | |
parent | c4ddab6ff23cefb07b06f2ab4e06773b82aa84e2 (diff) | |
download | bcm5719-llvm-52e4a0e109dd0428b40ae3b380616cd211b3a705.tar.gz bcm5719-llvm-52e4a0e109dd0428b40ae3b380616cd211b3a705.zip |
AVX-512: Added more intrinsics for convert and min/max.
Removed vzeroupper from AVX-512 mode - our optimization gude does not recommend to insert vzeroupper at all.
llvm-svn: 198557
Diffstat (limited to 'llvm/lib/Target/X86/X86VZeroUpper.cpp')
-rw-r--r-- | llvm/lib/Target/X86/X86VZeroUpper.cpp | 23 |
1 files changed, 7 insertions, 16 deletions
diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp index 66ae9c2d7f9..ec5c9da37e3 100644 --- a/llvm/lib/Target/X86/X86VZeroUpper.cpp +++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp @@ -17,6 +17,7 @@ #define DEBUG_TYPE "x86-vzeroupper" #include "X86.h" #include "X86InstrInfo.h" +#include "X86Subtarget.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -105,28 +106,20 @@ FunctionPass *llvm::createX86IssueVZeroUpperPass() { } static bool isYmmReg(unsigned Reg) { - return (Reg >= X86::YMM0 && Reg <= X86::YMM31); -} - -static bool isZmmReg(unsigned Reg) { - return (Reg >= X86::ZMM0 && Reg <= X86::ZMM31); + return (Reg >= X86::YMM0 && Reg <= X86::YMM15); } static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) { for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(), E = MRI.livein_end(); I != E; ++I) - if (isYmmReg(I->first) || isZmmReg(I->first)) + if (isYmmReg(I->first)) return true; return false; } static bool clobbersAllYmmRegs(const MachineOperand &MO) { - for (unsigned reg = X86::YMM0; reg <= X86::YMM31; ++reg) { - if (!MO.clobbersPhysReg(reg)) - return false; - } - for (unsigned reg = X86::ZMM0; reg <= X86::ZMM31; ++reg) { + for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) { if (!MO.clobbersPhysReg(reg)) return false; } @@ -155,11 +148,7 @@ static bool clobbersAnyYmmReg(MachineInstr *MI) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isRegMask()) continue; - for (unsigned reg = X86::YMM0; reg <= X86::YMM31; ++reg) { - if (MO.clobbersPhysReg(reg)) - return true; - } - for (unsigned reg = X86::ZMM0; reg <= X86::ZMM31; ++reg) { + for (unsigned reg = X86::YMM0; reg <= X86::YMM15; ++reg) { if (MO.clobbersPhysReg(reg)) return true; } @@ -170,6 +159,8 @@ static bool clobbersAnyYmmReg(MachineInstr *MI) { /// runOnMachineFunction - Loop over all of the basic blocks, inserting /// vzero upper instructions before function calls. bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) { + if (MF.getTarget().getSubtarget<X86Subtarget>().hasAVX512()) + return false; TII = MF.getTarget().getInstrInfo(); MachineRegisterInfo &MRI = MF.getRegInfo(); bool EverMadeChange = false; |