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authorKay Tiong Khoo <kkhoo@perfwizard.com>2013-02-14 19:08:21 +0000
committerKay Tiong Khoo <kkhoo@perfwizard.com>2013-02-14 19:08:21 +0000
commitf809c6491d34dc702d12eeec63b03303c87dca7f (patch)
treeeaed5e6f32076a8a1c29f4e38ed5ad68ab9b5185 /llvm/lib/Target/X86/X86Subtarget.h
parenta934a022af67bf1ed04db7b7d4f2eb1842bf94e4 (diff)
downloadbcm5719-llvm-f809c6491d34dc702d12eeec63b03303c87dca7f.tar.gz
bcm5719-llvm-f809c6491d34dc702d12eeec63b03303c87dca7f.zip
added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases llvm-svn: 175196
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.h')
-rw-r--r--llvm/lib/Target/X86/X86Subtarget.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h
index eb587a57613..1466041712e 100644
--- a/llvm/lib/Target/X86/X86Subtarget.h
+++ b/llvm/lib/Target/X86/X86Subtarget.h
@@ -121,6 +121,9 @@ protected:
/// HasRTM - Processor has RTM instructions.
bool HasRTM;
+ /// HasADX - Processor has ADX instructions.
+ bool HasADX;
+
/// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
bool IsBTMemSlow;
@@ -242,6 +245,7 @@ public:
bool hasBMI() const { return HasBMI; }
bool hasBMI2() const { return HasBMI2; }
bool hasRTM() const { return HasRTM; }
+ bool hasADX() const { return HasADX; }
bool isBTMemSlow() const { return IsBTMemSlow; }
bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
bool hasVectorUAMem() const { return HasVectorUAMem; }
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